NVM is now widely used for a variety of applications, since it may store information without continuously applied electric power, and by applying appropriate voltages, the NVM may be programmed or re-programmed (erased). Such a memory may provide a basic operating system or microcode for a logic device, such as a processor. A kind of NVM, embedded NVM in a CMOS device, allows a single chip produced by a manufacturer to be configured for various applications, and/or allows a single device to be configured by a user for different applications. Programming of the embedded NVM is typically done by downloading code from an external source, such as a computer.
However, many NVM processes require multiple layers of poly-silicon, while many conventional CMOS processes require only a single layer of poly-silicon. In order to embed this kind of NVM into a CMOS device, several additional processing steps are required. These additional processing steps result in increased processing time, higher cost of manufacturing, increased possibility of defects, and in turn result in lower yields. To address this problem, repair circuit regions on a die are included in some circuit designs in order to compensate for the reduced device yield. But valuable areas on the die are consumed by these repair circuits, further increasing the cost of manufacturing.
For example, a conventional 2-transistor EEPROM typically requires a high voltage (>15 Volts) in the bit line or word line diffusion to perform the erase and program operations. In addition, the conventional EEPROM cell structure creates manufacturing difficulties. As a result, the manufacturing cost of the conventional EEPROM is higher, the cell size is bigger, and the array density is limited to low density devices. Additionally, the complex topology of the conventional EEPROM cell also results in difficulties in alignment and scalability.
In another kind of EEPROM, stacked gate flash EEPROM, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. Unfortunately, the thin tunnel (or floating gate) oxide may easily impact the wafer yield, and creates problems concerning reliability in manufacturing process.
Yet another kind of flash memory, split gate flash, is desirable to achieve efficient programming through carrier injection at a lower programming voltage (about 12V). The injection efficiency is achieved at desirably low programming currents by applying a relatively large potential to a first gate and a relatively small potential to a second gate. However, the design of typical split-gate device has an adverse impact on the cell density (the amount of information that may be stored in a defined area), as the first and second gates both consumes precious wafer area.
Other NVM cell structures are proposed. U.S. Pat. No. 5,892,709 discloses a single level gate nonvolatile memory device, which is simple and inexpensive to fabricate. Further more, the single level gate NVM is efficient and reliable to be accessed. However, the applied voltages for program and erase operations are definitely too high.
U.S. Pat. No. 6,631,087 discloses a single polysilicon EEPROM memory device that operates at relatively low erase and program voltages and currents. Furthermore, single polysilicon EEPROM does not suffer from various disturbances during the program, read and erase operations. For programming the memory cell, a bias voltage of 5V is applied, while a bias voltage of approximately −5V is applied for erasing operation. However, the bias voltage range of +5V to −5V is still too large, and as known to those skilled in the art, the applied negative voltage will bring negative impact on its application in many aspects.
To overcome these problems listed above, there is a need for a NVM which is compatible with the CMOS process, uses lower voltages for operating, and is more reliable in program, read, or erase operation.